First Libero SoC Design Suite Release

Microchip announced the release of Libero SoC version 12.0, delivering new gains in runtime and quality of results, as well as one unified design suite for all the company’s latest-generation FPGA families, including new production releases of PolarFire FPGAs.
Libero SoC v12.0 reduces design flow runtimes and, with the improved quality of results, it provides results in fewer design iterations and improves customer productivity. By upgrading to Libero SoC v12.0, designers will see runtime reduction of 60 percent for timing, 25 percent for place and route and 18 percent for power results. They will also see an average increase of four percent in quality of results for larger designs and a 10 percent improvement for the PolarFire MPF300/TS-1 device.

Key Specifications:
This release supports the following features and enhancements:
• Unified Libero design suite for PolarFire, RTG4, SmartFusion2, and IGLOO2 FPGA families
• Device Support
• PolarFire Silicon Feature Enhancements
• Runtime and Memory Improvements compared to previous release (Libero SoC v11.9 and Libero SoC PolarFire v2.3)
• Design Performance Improvements
• Timing Constraints Enhancements (all families)
• Project Manager Enhancements
• Programming Solutions
• SmartDebug Enhancements

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